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\noindent
{\bf Amdahl Vector Processors (Fujitsu VP)}


\noindent
{\bf Vector Register Architecture}

\vspace {.1in}
\noindent
{\bf Architecture:}
The Amdahl 500, 1100, 1200, and 1400 Vector Processors are
marketed by Amdahl Corp. in the U.S., Canada, Europe, and the Pacific
Basin. These products are manufactured by Fujitsu, and similar
models are marketed in Japan as the VP-50, VP-100, VP-200,
and VP-400.  The VP-100 and 200 is also marketed by Siemens
in mainland Europe. In 1987, the range was upgraded by the
addition of E models. The main change was to the functional pipes.

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\noindent
These are all register-to-register machines.  All models
have one scalar and one vector unit which can execute
computations independently. The scalar unit fetches all
instructions and passes each instruction to the appropriate
unit for execution. The scalar processor is based on the
Fujitsu M380/382 series mainframes and runs the IBM S/370 extended
architecture instruction set. A recent Amdahl proprietary software
program product, called VP/XA, allows Amdahl vector processors to
run current MVS/XA releases, and permits Amdahl supercomputers to
use standard operating environments.

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\noindent
{\bf Configuration:}
The vector unit consists of 5 or 6 pipelines, a vector
register memory, and a mask memory. The 5 or 6 pipelines
comprise 1 or 2 load/store pipelines, plus 1 mask pipeline,
1 add/logical pipeline, 1 multiply pipeline, and 1 divide
pipeline.
In the E models, the multiply pipe is replaced by a
multifunctional pipe for floating-point addition, multiplication,
or concurrent multiplication/addition.
The number of concurrent pipelines, vector
register size, and mask register size differ for each model,
as shown below. Main memory capacity ranges from 32 Mbytes
to 1024 Mbytes (4 to 128 M 64-bit words).

\vspace{.15in}
\begin{center}
\begin {tabular} {l r r r r}
&amp; \multicolumn{4} {c}{Model} \\
Configuration &amp; 500  &amp;  1100  &amp; 1200  &amp; 1400  \\
\hline
\# pipes total &amp;  5  &amp;     6  &amp;     6  &amp;     5 \\
\# concurrent load/store pipes &amp; 1 &amp;     2  &amp;     2   &amp;    1 \\
\# 64 bit words/vect cyc/pipe &amp; 1   &amp;    1  &amp;     2   &amp;    4 \\
Scalar cycle time (nsec)&amp;  14  &amp;    14  &amp;    14  &amp;    14 \\
Vector cycle time (nsec)&amp;  7  &amp;   7 &amp;    7 &amp;    7 \\
\# concurrent arith pipes &amp;     2  &amp;     3  &amp;     3  &amp;     3 \\
\# 64-bit results/vect cyc/pipe &amp; 1 &amp;    1  &amp;     2  &amp;     4 \\
Vect. reg. size (Kbytes)    &amp;    32   &amp;   32  &amp;    64  &amp;    128 \\
Mask reg. size (Bytes) &amp; 512  &amp;   512  &amp;   1024 &amp;   2048 \\
Max. main memory (Mbytes)    &amp;   512  &amp;   512  &amp;  1024  &amp;  1024 \\
Min. main memory (Mbytes)   &amp;    32  &amp;    32   &amp;   64   &amp;   64 \\
Max. interleaving (ways) &amp; 128  &amp;   128  &amp;   256  &amp;   256 \\
\end{tabular}
\end{center}
\vspace{.15in}

The total vector register capacity is 32-128 Kbytes.
The registers can be reconfigured dynamically to 6 different
combinations with varying vector register lengths, as shown below:

\vspace{.15in}
\begin{center}
\begin {tabular} {l r r r r}
\multicolumn{5} {c}{Configuration of Vector Registers}\\
&amp; \multicolumn{4} {c}{ Register Length by Model} \\
&amp; \multicolumn{4}  {c}{(\# of 64-bit word elements)} \\
\# registers &amp; 500 &amp;   1100  &amp; 1200  &amp; 1400 \\
\hline
8   &amp;   512  &amp;  512  &amp;  1024 &amp;  2048 \\
16  &amp;   256  &amp;  256  &amp;  512  &amp;  1024 \\
32  &amp;   128  &amp;  128  &amp;  256  &amp;  512 \\
64  &amp;   64  &amp;   64  &amp;   128  &amp;  256 \\
128 &amp;   32  &amp;   32  &amp;   64  &amp;   128 \\
256 &amp;   16  &amp;   16  &amp;   32  &amp;   64 \\
\end{tabular}
\end{center}
\vspace{.15in}

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\noindent
Other features:
\begin{tabbing}
aaa\=  \kill
\&gt;  400 and 1300 gate ECL, 350-picosecond delay\\
\&gt;  main memory - 256 KB, 55 nsec, MOS static RAM\\
\&gt;  380-470 square feet\\
\&gt;  36-62 KVA power consumption\\
\&gt;  air cooled
\end{tabbing}


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\noindent
{\bf Performance:}
\vspace{.1in}
\noindent
The vector performance varies according to model as
follows:

\vspace{.15in}
\begin{center}
\begin {tabular} {c c c c}
Model &amp; Peak Mflops &amp; Model &amp;  Peak Mflops \\
\hline
500 &amp; 143 &amp; 500E &amp;  286 \\
1100 &amp;  286 &amp;  1100E &amp;  429 \\
1200 &amp;  571 &amp;  1200E &amp;  857 \\
1400 &amp;  1143 &amp;  1400E &amp;  1714 \\
2000 &amp;  1600+  &amp;      &amp;   
\end{tabular}
\end{center}
\vspace{.15in}

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\noindent
The scalar processor cycle time is 14 nsec,
compared to the CRAY X-MP's 8.5 nsec, but a sampling of
scalar instructions indicates that the VP operations may be
slightly faster than the X-MP's.
All scalar work can overlap vector
operations.

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\noindent
{\bf Software:}
\vspace{.1in}
\noindent
\begin{tabbing}
aaa\=  \kill
\&gt;  VP/XA operating system offering IBM MVS/XA system support\\
\&gt;  Automatic vectorizing Fortran compiler (Fortran 77/VP)\\
\&gt;  Scalar Fortran compiler\\
\&gt;  Interactive debugger\\
\&gt;  Performance measurement tools\\
\&gt;  Interactive vectorizer\\
\&gt;  STREAM77 Language Converter\\
\&gt;  SIMUL38 IBM 3838 array processor simulator\\
\&gt;  Scientific subroutine library (223 routines)
\end{tabbing}


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\noindent
{\bf Contact:}
\vspace{.1in}
\begin{flushleft}
Phil Howell \\
Amdahl Corp. \\
1250 East Arques Ave. \\
P.O. Box 3470 \\
Sunnyvale, CA 94088 \\
408-746-6880 \\
 
\vspace {.1in}
Dr. Horst-Peter Rother \\
Amdahl International Management Services Ltd. \\
Dogmersfield Park \\
Hartley Wintney \\
Hampshire RG27 8TE \\
England\\
0252-24555   Telex 858486 G 
\end{flushleft}

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